Persistent Link: https://ieeexplore.ieee.org/servlet/opac?punumber=4 ...

Presently, he is engaged in Block Level Implementation for a Networking ASIC chip at 7nm FinFET technology, where his accountabilities include the Block level APR, and complete Sign-off closure for ...

Achieving system-on-chip (SoC) timing closure is a major obstacle in the FinFET era. Even though designers can now use faster transistors that consume and leak less power than before, FinFET ...

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage,Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.