How the RISC-V architecture’s inherent traits align with the demands of functional safety standards like ISO 26262.
A new technical paper titled “Optimizing Energy Efficiency in Subthreshold RISC-V Cores” was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract “Our goal in ...
The ISRO Inertial Systems Unit (IISU) in Thiruvananthapuram initiated the development of a 64-bit RISC-V-based controller and ...
Collaboration milestone addresses key pain points of typical design verification, the open silicon ecosystem organisation, ...
IIT Madras develops indigenous Shakti semiconductor chip for ISRO, marking a milestone in Make in India efforts.
New Delhi: Indian Institute of Technology (IIT) Madras and ISRO have developed an indigenous microprocessor for space ...
New variants in the u-blox Nora-B2 Bluetooth LE 6.0 module family integrate Nordic’s entire nRF54L series of ultra-low power ...
IIT Madras and ISRO developed and tested the SHAKTI-based IRIS chip for aerospace applications, promoting indigenized ...
(GLOBE NEWSWIRE) -- lowRISC C.I.C., the open silicon ecosystem organisation, today announced the addition of formal ...
The UK-based chip designer pivots to selling its own chips, securing Meta as its first major customer, and challenging ...
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